1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a Delay Locked Loop (DLL) generating an internal clock signal.
2. Discussion of Related Art
In general, mobile products such as camcorders, digital cameras, cell phones, MP3 (MPEG-1 Layer3) players, or the like should operate for a long time with a low power, so that consumed powers of the semiconductor devices included in the mobile products should be decreased. Meanwhile, the DLL includes a plurality of delay units which consume a relatively large amount of currents, so that its consumed power increases at the time of locking operation of the DLL. Accordingly, in the case of the semiconductor device including the DLL, the consumed power of the DLL takes up a relatively large amount of the total consumed power of the semiconductor device. Consequently, when the consumed power of the DLL decreases, the total consumed power of the semiconductor device can be significantly decreased. Accordingly, when the semiconductor device enters into a power down mode (or a standby mode) in order to decrease the consumed power of the semiconductor device including the DLL, the DLL can be designed to be disabled. However, when a time (e.g., 7 μs or 8 μs) taken for maintaining the semiconductor device in the power down mode increases, a time taken for the DLL to carry out the locking operation again increases in an active mode after the power down mode. This is because that the DLL, when it enters into the power down mode, is disabled while maintaining the previous locking state. Accordingly, when a phase of an external clock signal before the power down mode becomes different from a phase of the external clock signal after the power down mode, a phase difference between the external clock signal and an internal clock signal occurring while the DLL is locked in the previous locking state significantly increases out of the predetermined range after the power down mode. In this case, the DLL carries out the locking operation so as to make the internal clock signal synchronized with the changed external clock signal, and the locking operation time of the DLL increases when the phase difference between the internal clock signal and the external clock signal increases. That is, the time taken for having the DLL locked increases. As such, when the locking operation time of the DLL increases, an operational speed of the semiconductor device decreases, and an operational performance of the semiconductor device is degraded. Such a phenomenon may be more severe when the time taken for maintaining the semiconductor device in the power down mode increases (i.e., when the time taken for disabling the DLL increases). The DLL may be designed to keep an enabled state even when the semiconductor device enters into the power down mode (or standby mode) in order to increase the operational speed of the semiconductor device including the DLL. However, when the DLL is continuously enabled, the consumed power of the DLL increases, so that the total consumed power of the semiconductor device increases.